View M27C2001-90XK6TR_6675663.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1/17 september 2000 m27c2001 2 mbit (256kb x 8) uv eprom and otp eprom n 5v 10% supply voltage in read operation n access time: 55ns n low power consumption: active current 30ma at 5mhz standby current 100 m a n programming voltage: 12.75v 0.25v n programming time: 100 m s/word n electronic signature manufacturer code: 20h device code: 61h description the m27c2001 is a high speed 2 mbit eprom of- fered in the two ranges uv (ultra violet erase) and otp (one time programmable). it is ideally suited for microprocessor systems requiring large pro- grams and is organised as 262,144 by 8 bits. the fdip32w (window ceramic frit-seal package) and lccc32w (leadless chip carrier package) have a transparent lids which allow the user to ex- pose the chip to ultraviolet light to erase the bit pat- tern. a new pattern can then be written to the device by following the programming procedure. for applications where the content is programmed only one time and erasure is not required, the m27c2001 is offered in pdip32, plcc32 and tsop32 (8 x 20 mm) packages. figure 1. logic diagram ai00716b 18 a0-a17 p q0-q7 v pp v cc m27c2001 g e v ss 8 1 32 32 1 fdip32w (f) pdip32 (b) plcc32 (k) tsop32 (n) 8 x 20 mm lccc32w (l)
m27c2001 2/17 figure 2b. lcc connections ai00718 a17 a8 a10 q5 17 a1 a0 q0 q1 q2 q3 q4 a7 a4 a3 a2 a6 a5 9 p a9 1 a16 a11 a13 a12 q7 32 v pp v cc m27c2001 a15 a14 q6 g e 25 v ss figure 2a. dip connections a1 a0 q0 a7 a4 a3 a2 a6 a5 a13 a10 a8 a9 q7 a14 a11 g e q5 q1 q2 q3 v ss q4 q6 a17 p a16 a12 v pp v cc a15 ai00717 m27c2001 8 1 2 3 4 5 6 7 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 figure 2c. tsop connections a1 a0 q0 a7 a4 a3 a2 a6 a5 a13 a10 a8 a9 q7 a14 a11 g e q5 q1 q2 q3 q4 q6 a17 p a16 a12 v pp v cc a15 ai01153b m27c2001 (normal) 8 1 9 16 17 24 25 32 v ss table 1. signal names a0-a17 address inputs q0-q7 data outputs e chip enable g output enable p program v pp program supply v cc supply voltage v ss ground
3/17 m27c2001 table 2. absolute maximum ratings (1) note: 1. except for the rating ooperating temperature rangeo, stresses above those listed in the table oabsolute maximum ratingso may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant qual- ity documents. 2. minimum dc voltage on input or output is 0.5v with possible undershoot to 2.0v for a period less than 20ns. maximum dc voltage on output is v cc +0.5v with possible overshoot to v cc +2v for a period less than 20ns. 3. depends on range. table 3. operating modes note: x = v ih or v il ,v id = 12v 0.5v. table 4. electronic signature symbol parameter value unit t a ambient operating temperature (3) 40 to 125 c t bias temperature under bias 50 to 125 c t stg storage temperature 65 to 150 c v io (2) input or output voltage (except a9) 2 to 7 v v cc supply voltage 2 to 7 v v a9 (2) a9 voltage 2 to 13.5 v v pp program supply voltage 2 to 14 v mode e g p a9 v pp q7-q0 read v il v il xx v cc or v ss data out output disable v il v ih xxv cc or v ss hi-z program v il v ih v il pulse x v pp data in verify v il v il v ih xv pp data out program inhibit v ih xxx v pp hi-z standby v ih xxx v cc or v ss hi-z electronic signature v il v il v ih v id v cc codes identifier a0 q7 q6 q5 q4 q3 q2 q1 q0 hex data manufacturer's code v il 00100000 20h device code v ih 01100001 61h
m27c2001 4/17 device operation the operating modes of the m27c2001 are listed in the operating modes table. a single power sup- ply is required in the read mode. all inputs are ttl levels except for v pp and 12v on a9 for electronic signature. read mode the m27c2001 has two control functions, both of which must be logically active in order to obtain data at the outputs. chip enable (e) is the power control and should be used for device selection. output enable (g) is the output control and should be used to gate data to the output pins, indepen- dent of device selection. assuming that the ad- dresses are stable, the address access time (t avqv ) is equal to the delay from e to output (t elqv ). data is available at the output after a delay of t glqv from the falling edge of g, assuming that e has been low and the addresses have been sta- ble for at least t avqv -t glqv . standby mode the m27c2001 has a standby mode which reduc- es the supply current from 30ma to 100 m a. the m27c2001 is placed in the standby mode by ap- plying a cmos high signal to the e input. when in the standby mode, the outputs are in a high imped- ance state, independent of the g input. table 5. ac measurement conditions high speed standard input rise and fall times 10ns 20ns input pulse voltages 0 to 3v 0.4v to 2.4v input and output timing ref. voltages 1.5v 0.8v and 2v figure 3. ac testing input output waveform ai01822 3v high speed 0v 1.5v 2.4v standard 0.4v 2.0v 0.8v figure 4. ac testing load circuit ai01823b 1.3v out c l c l = 30pf for high speed c l = 100pf for standard c l includes jig capacitance 3.3k w 1n914 device under test table 6. capacitance (1) (t a =25 c, f = 1 mhz) note: 1. sampled only, not 100% tested. symbol parameter test condit ion min max unit c in input capacitance v in =0v 6pf c out output capacitance v out =0v 12 pf
5/17 m27c2001 table 7. read mode dc characteristics (1) (ta = 0 to 70 c or 40 to 85 c; v cc =5v 5% or 5v 10%; v pp =v cc ) note: 1. v cc must be applied simultaneously with or before v pp and removed simultaneously or after v pp . 2. maximum dc voltage on output is v cc +0.5v. table 8a. read mode ac characteristics (1) (ta = 0 to 70 c or 40 to 85 c; v cc =5v 5% or 5v 10%; v pp =v cc ) note: 1. v cc must be applied simultaneously with or before v pp and removed simultaneously or after v pp . 2. sampled only, not 100% tested. 3. in case of 45ns speed see high speed ac measurement conditions. symbol parameter test condition min max unit i li input leakage current 0v v in v cc 10 m a i lo output leakage current 0v v out v cc 10 m a i cc supply current e=v il ,g=v il , i out = 0ma, f = 5mhz 30 ma i cc1 supply current (standby) ttl e=v ih 1ma i cc2 supply current (standby) cmos e > v cc 0.2v 100 m a i pp program current v pp =v cc 10 m a v il input low voltage 0.3 0.8 v v ih (2) input high voltage 2 v cc +1 v v ol output low voltage i ol = 2.1ma 0.4 v v oh output high voltage ttl i oh = 400 m a 2.4 v output high voltage cmos i oh = 100 m av cc 0.7v v symbol alt parameter test condition m27c2001 unit -55 (3) -70 -80 -90 min max min max min max min max t avqv t acc address valid to output valid e=v il ,g=v il 55 70 80 90 ns t elqv t ce chip enable low to output valid g=v il 55 70 80 90 ns t glqv t oe output enable low to output valid e=v il 30 35 40 40 ns t ehqz (2) t df chip enable high to output hi-z g=v il 0 30 0 30 0 30 0 30 ns t ghqz (2) t df output enable high to output hi-z e=v il 0 30 0 30 0 30 0 30 ns t axqx t oh address transition to output transition e=v il ,g=v il 0000ns two line output control because eproms are usually used in larger memory arrays, this product features a 2 line con- trol function which accommodates the use of mul- tiple memory connection. the two line control function allows: a. the lowest possible memory power dissipation, b. complete assurance that output bus contention will not occur. for the most efficient use of these two control lines, e should be decoded and used as the prima- ry device selecting function, while g should be made a common connection to all devices in the array and connected to the read line from the system control bus. this ensures that all deselect- ed memory devices are in their low power standby mode and that the output pins are only active when data is required from a particular memory device.
m27c2001 6/17 figure 5. read mode ac waveforms ai00719b taxqx tehqz a0-a17 e g q0-q7 tavqv tghqz tglqv telqv valid hi-z valid table 8b. read mode ac characteristics (1) (ta = 0 to 70 c or 40 to 85 c; v cc =5v 5% or 5v 10%; v pp =v cc ) note: 1. v cc must be applied simultaneously with or before v pp and removed simultaneously or after v pp . 2. sampled only, not 100% tested. symbol alt parameter test condition m27c2001 unit -10 -12 -15/-20/-25 min max min max min max t avqv t acc address valid to output valid e=v il ,g=v il 100 120 150 ns t elqv t ce chip enable low to output valid g=v il 100 120 150 ns t glqv t oe output enable low to output valid e=v il 50 50 60 ns t ehqz (2) t df chip enable high to output hi-z g=v il 030040050ns t ghqz (2) t df output enable high to output hi-z e=v il 030040050ns t axqx t oh address transition to output transition e=v il ,g=v il 000ns system considerations the power switching characteristics of advanced cmos eproms require careful decoupling of the devices. the supply current, i cc , has three seg- ments that are of interest to the system designer: the standby current level, the active current level, and transient current peaks that are produced by the falling and rising edges of e. the magnitude of the transient current peaks is dependent on the capacitive and inductive loading of the device at the output. the associated transient voltage peaks can be suppressed by complying with the two line output control and by properly selected decoupling capacitors. it is recommended that a 0.1 m f ceram- ic capacitor be used on every device between v cc and v ss . this should be a high frequency capaci- tor of low inherent inductance and should be placed as close to the device as possible. in addi- tion, a 4.7 m f bulk electrolytic capacitor should be used between v cc and v ss for every eight devic- es. the bulk capacitor should be located near the power supply connection point. the purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of pcb traces.
7/17 m27c2001 table 9. programming mode dc characteristics (1) (t a =25 c; v cc = 6.25v 0.25v; v pp = 12.75v 0.25v) note: 1. v cc must be applied simultaneously with or before v pp and removed simultaneously or after v pp . table 10. programming mode ac characteristics (1) (t a =25 c; v cc = 6.25v 0.25v; v pp = 12.75v 0.25v) note: 1. v cc must be applied simultaneously with or before v pp and removed simultaneously or after v pp . 2. sampled only, not 100% tested. symbol parameter test condition min max unit i li input leakage current 0 v in v ih 10 m a i cc supply current 50 ma i pp program current e=v il 50 ma v il input low voltage 0.3 0.8 v v ih input high voltage 2 v cc + 0.5 v v ol output low voltage i ol = 2.1ma 0.4 v v oh output high voltage ttl i oh = 400 m a 2.4 v v id a9 voltage 11.5 12.5 v symbol alt parameter test condition min max unit t avpl t as address valid to program low 2 m s t qvpl t ds input valid to program low 2 m s t vphpl t vps v pp high to program low 2 m s t vchpl t vcs v cc high to program low 2 m s t elpl t ces chip enable low to program low 2 m s t plph t pw program pulse width 95 105 m s t phqx t dh program high to input transition 2 m s t qxgl t oes input transition to output enable low 2 m s t glqv t oe output enable low to output valid 100 ns t ghqz (2) t dfp output enable high to output hi-z 0 130 ns t ghax t ah output enable high to address transition 0ns programming when delivered (and after each erasure for uv eprom), all bits of the m27c2001 are in the '1' state. data is introduced by selectively program- ming '0's into the desired bit locations. although only '0's will be programmed, both '1's and '0's can be present in the data word. the only way to change a '0' to a '1' is by die exposure to ultraviolet light (uv eprom). the m27c2001 is in the pro- gramming mode when v pp input is at 12.75v, e is at v il and p is pulsed to v il . the data to be pro- grammed is applied to 8 bits in parallel to the data output pins. the levels required for the address and data inputs are ttl. v cc is specified to be 6.25v 0.25v.
m27c2001 8/17 presto ii programming algorithm presto ii programming algorithm allows the whole array to be programmed with a guaranteed margin, in a typical time of 26.5 seconds. pro- gramming with presto ii consists of applying a sequence of 100 m s program pulses to each byte until a correct verify occurs (see figure 7). during programming and verify operation, a margin mode circuit is automatically activated in order to guarantee that each cell is programmed with enough margin. no overprogram pulse is applied since the verify in margin mode provides the necessary margin to each programmed cell. program inhibit programming of multiple m27c2001s in parallel with different data is also easily accomplished. ex- cept for e, all like inputs including g of the parallel m27c2001 may be common. a ttl low level pulse applied to a m27c2001's p input, with e low and v pp at 12.75v, will program that m27c2001. a high level e input inhibits the other m27c2001s from being programmed. program verify a verify (read) should be performed on the pro- grammed bits to determine that they were correct- ly programmed. the verify is accomplished with e and g at v il , p at v ih ,v pp at 12.75v and v cc at 6.25v. figure 6. programming and verify modes ac waveforms tavpl valid ai00720 a0-a17 q0-q7 v pp v cc p g data in data out e tqvpl tvphpl tvchpl tphqx tplph tglqv tqxgl telpl tghqz tghax program verify figure 7. programming flowchart ai00715c n=0 last addr verify p = 100 m s pulse ++n =25 ++ addr v cc = 6.25v, v pp = 12.75v fail check all bytes 1st: v cc =6v 2nd: v cc = 4.2v yes no yes no yes no
9/17 m27c2001 electronic signature the electronic signature (es) mode allows the reading out of a binary code from an eprom that will identify its manufacturer and type. this mode is intended for use by programming equipment to automatically match the device to be programmed with its corresponding programming algorithm. the es mode is functional in the 25 c 5 c am- bient temperature range that is required when pro- gramming the m27c2001. to activate the es mode, the programming equipment must force 11.5v to 12.5v on address line a9 of the m27c2001 with v pp =v cc = 5v. two identifier bytes may then be sequenced from the device out- puts by toggling address line a0 from v il to v ih . all other address lines must be held at v il during electronic signature mode. byte 0 (a0 = v il ) rep- resents the manufacturer code and byte 1 (a0 = v ih ) the device identifier code. for the stmicroelectronics m27c2001, these two identifi- er bytes are given in table 4 and can be read-out on outputs q7 to q0. erasure operation (applies to uv eprom) the erasure characteristics of the m27c2001 are such that erasure begins when the cells are ex- posed to light with wavelengths shorter than ap- proximately 4000 ?. it should be noted that sunlight and some type of fluorescent lamps have wavelengths in the 3000-4000 ? range. data shows that constant exposure to room level fluo- rescent lighting could erase a typical m27c2001 in about 3 years, while it would take approximately 1 week to cause erasure when exposed to direct sunlight. if the m27c2001 is to be exposed to these types of lighting conditions for extended pe- riods of time, it is suggested that opaque labels be put over the m27c2001 window to prevent unin- tentional erasure. the recommended erasure pro- cedure for the m27c2001 is exposure to short wave ultraviolet light which has wavelength of 2537 ?. the integrated dose (i.e. uv intensity x exposure time) for erasure should be a minimum of 15 w-sec/cm 2 . the erasure time with this dos- age is approximately 15 to 20 minutes using an ul- traviolet lamp with 12000 m w/cm 2 power rating. the m27c2001 should be placed within 2.5 cm (1 inch) of the lamp tubes during the erasure. some lamps have a filter on their tubes which should be removed before erasure.
m27c2001 10/17 table 11. ordering information scheme note: 1. high speed, see ac characteristics section for further information. 2. these speeds are replaced by the 100ns. for a list of available options (speed, package, etc...) or for further information on any aspect of this de- vice, please contact the stmicroelectronics sales office nearest to you. example: m27c2001 -55 x c 1 x device type m27 supply voltage c=5v device function 2001 = 2 mbit (256kb x 8) speed -55 (1) =55ns -70 = 70 ns -80 = 80 ns -90 = 90 ns -10 = 100 ns not for new design (2) -12 = 120 ns -15 = 150 ns -20 = 200 ns -25 = 250 ns v cc tolerance x= 5% blank = 10% package f = fdip32w b = pdip32 l = lccc32w k = plcc32 n = tsop32: 8 x 20 mm temperature range 1=0to70 c 6=40to85 c optio ns x = additional burn-in tr = tape & reel packing
11/17 m27c2001 table 12. revision history date revision details june 1998 first issue 09/20/00 an620 reference removed
m27c2001 12/17 table 13. fdip32w - 32 pin ceramic frit-seal dip, with window, package mechanical data symbol mm inches typ min max typ min max a 5.72 0.225 a1 0.51 1.40 0.020 0.055 a2 3.91 4.57 0.154 0.180 a3 3.89 4.50 0.153 0.177 b 0.41 0.56 0.016 0.022 b1 1.45 0.057 c 0.23 0.30 0.009 0.012 d 41.73 42.04 1.643 1.655 d2 38.10 1.500 e 15.24 0.600 e1 13.06 13.36 0.514 0.526 e 2.54 0.100 ea 14.99 0.590 eb 16.18 18.03 0.637 0.710 l 3.18 0.125 s 1.52 2.49 0.060 0.098 ? 7.11 0.280 a 4 11 4 11 n32 32 figure 8. fdip32w - 32 pin ceramic frit-seal dip, with window, package outline drawing is not to scale. fdipw-a a3 a1 a l b1 b e d s e1 e n 1 c a ea d2 ? eb a2
13/17 m27c2001 table 14. pdip32 - 32 lead plastic dip, 600 mils width, package mechanical data symbol mm inches typ min max typ min max a 5.08 0.200 a1 0.38 0.015 a2 3.56 4.06 0.140 0.160 b 0.38 0.51 0.015 0.020 b1 1.52 0.060 c 0.20 0.30 0.008 0.012 d 41.78 42.04 1.645 1.655 d2 38.10 1.500 e 15.24 0.600 e1 13.59 13.84 0.535 0.545 e1 2.54 0.100 ea 15.24 0.600 eb 15.24 17.78 0.600 0.700 l 3.18 3.43 0.125 0.135 s 1.78 2.03 0.070 0.080 a 0 10 0 10 n32 32 figure 9. pdip32 - 32 lead plastic dip, 600 mils width, package outline drawing is not to scale. pdip a2 a1 a l b1 b e1 d s e1 e n 1 c a ea eb d2
m27c2001 14/17 table 15. lccc32w - 32 lead leadless ceramic chip carrier, package mechanical data symbol mm inches typ min max typ min max a 2.28 0.090 b 0.51 0.71 0.020 0.028 d 11.23 11.63 0.442 0.458 e 13.72 14.22 0.540 0.560 e 1.27 0.050 e1 0.39 0.015 e2 7.62 0.300 e3 10.16 0.400 h 1.02 0.040 j 0.51 0.020 l 1.14 1.40 0.045 0.055 l1 1.96 2.36 0.077 0.093 k 10.50 10.80 0.413 0.425 k1 8.03 8.23 0.316 0.324 n32 32 figure 10. lccc32w - 32 lead leadless ceramic chip carrier, package outline drawing is not to scale. lcccw-a e3 1 n l1 b l hx45 o jx45 o e2 e e1 a d e k k1
15/17 m27c2001 table 16. plcc32 - 32 lead plastic leaded chip carrier, package mechanical data symbol millimeters inches typ min max typ min max a 2.54 3.56 0.100 0.140 a1 1.52 2.41 0.060 0.095 a2 0.38 0.015 b 0.33 0.53 0.013 0.021 b1 0.66 0.81 0.026 0.032 d 12.32 12.57 0.485 0.495 d1 11.35 11.56 0.447 0.455 d2 9.91 10.92 0.390 0.430 e 1.27 0.050 e 14.86 15.11 0.585 0.595 e1 13.89 14.10 0.547 0.555 e2 12.45 13.46 0.490 0.530 f 0.00 0.25 0.000 0.010 r 0.89 0.035 n32 32 nd 7 7 ne 9 9 cp 0.10 0.004 figure 11. plcc32 - 32 lead plastic leaded chip carrier, package outline drawing is not to scale. plcc d ne e1 e 1n d1 nd cp b d2/e2 e b1 a1 a r 0.51 (.020) 1.14 (.045) f a2
m27c2001 16/17 figure 12. tsop32 - 32 lead plastic thin small outline, 8 x 20 mm, package outline drawing is not to scale. tsop-a d1 e 1n cp b e a2 a n/2 d die c l a1 a table 17. tsop32 - 32 lead plastic thin small outline, 8 x 20 mm, package mechanical data symb mm inches typ min max typ min max a 1.20 0.047 a1 0.05 0.15 0.002 0.007 a2 0.95 1.05 0.037 0.041 b 0.15 0.27 0.006 0.011 c 0.10 0.21 0.004 0.008 d 19.80 20.20 0.780 0.795 d1 18.30 18.50 0.720 0.728 e 7.90 8.10 0.311 0.319 e 0.50 - - 0.020 - - l 0.50 0.70 0.020 0.028 a 0 5 0 5 n32 32 cp 0.10 0.004
17/17 m27c2001 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in lif e support devices or systems without express written approval of stmicroelectronics. the st logo is registered trademark of stmicroelectronics ? 2000 stmicroelectronics - all rights reserved all other names are the property of their respective owners. stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a . http://w ww.st.com

▲Up To Search▲

Price & Availability of M27C2001-90XK6TR

	To Download M27C2001-90XK6TR Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .